Digital IC Verification Engineer

ESPJOBS — Wed, 28 Aug 2024 09:43:37 +0000

Language English

Job Number:

010

Description:

Position Responsibilities

1. Develop verification plans based on design-related documentation, set up the verification environment, and complete verification from module level to system level.

2. Execute regression testing and enhance verification coverage.

3. Collaborate with chip design engineers to identify and resolve design defects.

4. Guide the design team in implementing a verification-friendly design flow.

5. Perform RTL-level, gate-level, and low-power verification with UPF (Unified Power Format).

6. Assist FPGA engineers and software engineers in completing FPGA prototype testing.

7. Ensure the integrity and correctness of chip designs from multiple dimensions.

Position Requirements

1. Bachelor’s degree or higher in Computer Science, Electrical Engineering, Communications Engineering, or related fields. 3+ years of work experience.

2. Experience in design or verification of peripheral modules, communication modules, or SoC systems.

3. Proficiency in Verilog and expertise in C/SystemVerilog.

4. Knowledge of one or more scripting languages such as Python, Ruby, Perl, Shell, Tcl, or Makefile.

5. Experience with UVM (Universal Verification Methodology) is a plus.

6. Familiarity with the digital chip development process and successful tape-out project experience is an advantage.

7. Experience with formal verification is a plus.

classification:

Corporate

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Shanghai

Suzhou

Singapore

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recruit.sgpr@fehuvi.com

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Digital IC Verification Engineer

ESPJOBS — Mon, 01 Jan 2024 16:06:00 +0000

Job Function:

SoC

Language English

locations:

Shanghai

Job Number:

Description:

Responsibilities

1. Develop verification programs and define the verification environment according to design documentation, in order to conduct module- to chip-level verification.

2. Perform regression tests to improve verification coverage.

3. Assist the FPGA and software teams in FPGA prototype testing.

4. Collaborate with chip design engineers to find and fix any design defects.

5. Ensure the integrity of chip designs by supervising the design department when building verifiable design processes.

6. Carry out door-level simulation, with UPF verification methodology, to ensure successful chip tapeout.

Qualifications

1. Bachelor’s degree, or above, in Computer Engineering/Electronic Engineering/Communications Engineering, or other related disciplines.

2. 3+ years of work experience.

3. Familiarity with SoC and communication theory.

4. Familiarity with Verilog, proficiency in C/System Verilog verification.

5. Proficiency in Perl/Shell/Tcl scripts.

6. Experience in FPGA verification and/or chip tapeout is a plus.

7. Familiarity with VMM/UVM is a plus.

classification:

Corporate

Job Function Select:

Job locations Select:

Shanghai

Suzhou

Job Status:

Hide

Resume Inbox:

recruit@fehuvi.com

Job Sort:

Espressif Systems - Suzhou

Digital IC Verification Engineer

Digital IC Verification Engineer